Single and multiple silicon chip packages, or semiconductor chip packages, are used to provide electrical connection between semiconductor chips and other electronic components in an electronic circuit, such as die-to-package or chip-to-board interconnects. These single and multiple chip packages serve as a substrate to securely anchor electronic components and as a pathway for electrical signals.
A major shortcoming with conventional single and multiple chip packages relates to high density area array interconnect systems, with a large number of connection points for very small components. More particularly, as operating speeds increase in digital and analog systems, the size and performance of single and multiple chip packages become more and more critical. In this regard, integrated circuit densities and I/O counts are increasing rapidly, forcing packages to have higher via and wiring densities. Further, the future direction of both chip and package assembly is away from traditional peripheral chip bonds and package pins and towards area array attachment techniques.
Newer technologies, such as area array attachment techniques, are driving engineers to design chip packages that more closely match the coefficient of thermal expansion (CTE) of silicon, or otherwise ensure the reliability of such packages through thermal cycling. Embracing and, in some cases over-riding, these trends is a constant drive in the electronics industry to improve performance and simultaneously reduce cost.
Most conventional single and multiple chip packages are typically constructed from thick, mechanically robust dielectric materials, such as ceramics (e.g., alumina, aluminum nitride, beryllium oxide, cordierite, and mullite) and reinforced organic laminates (e.g., epoxies with woven glass, polyimides with woven glass, and cyanate ester with woven glass). In some cases, materials are combined to produce certain improved properties, for example, a package may have a ceramic base with one or several thin films of polyimides or benzocyclobutane (BCB) disposed thereupon.
The most common single or multiple chip electronic packages are made from injection molded plastics with metal lead frames. Sometimes, these packages include laminated interconnect structures where the dielectric layers tare made from various resins, such as those used to make the commercially available "FR-4" board.
Recently, advances have been made with these laminated structures to somewhat increase density and performance, as in the case of laminated ball grid array packages. Such packages have a number of advantages over ceramic packages, such as typically lower cost, wide availability, lower dielectric constant, lower resistivity conduction paths, and lighter weight.
Unfortunately, these packages have disadvantages that offset the positive aspects of the material. These disadvantages include relatively larger via diameters, relatively low wiring densities, low via densities, high via capacitance, poor CTE match to silicon, non-flatness, large package size, poor thermal stability (glass transition T.sub.g.ltoreq.140.degree. C.), poor thermal conduction, and thick packages.
Some of these deficiencies have been addressed with the use of thin film polyimides and/or BCBs on ceramics. These materials have high via and wiring densities, small size, and lower dielectric constant. Despite these advantages, these materials still suffer from many shortcomings including high cost, highly resistive conduction paths, lower characteristic impedance, and processing problems leading to limited manufacturing sources and long lead times.
In an attempt to address the industry need for superior price-performance in single and multiple chip packages, packaging technologies have been developed which are based on thin dielectrics that are not reinforced with glass fibers or other mechanical aids. Examples of these thin dielectrics include thin polyimides and polytetrafluoroethylene (PTFE) based dielectrics, such as ceramic filled PTFE or cyanate ester impregnated porous PTFE. Compared with the conventional materials described hereinabove, these packaging technologies yield superior via and wiring density, extremely low dielectric constants, lower via capacitance, lower resistance, smaller package size, thinner packages, CTE matching over a wide range, lower package weight, greater thermal stability, and higher reliability than competing technologies.
In some cases, thin dielectrics are used that contain reinforcing materials such as woven glass. Notwithstanding such advantages, these technologies are impaired by very thin, fragile packages. For example, while typical ceramic packaging has a modulus of elasticity value of 40-50.times.10.sup.6 psi, a in- typical modulus for a ceramic filled PTFE based package is only about 100,000 psi. Due to these constraints, packaging made from this material is very difficult to handle and assemble. Mechanical stiffeners have been used with thin packages made with these materials to give them the needed mechanical robustness.
Another area of growing interest is in providing electronic packaging that provides critical electrical performance and cost enhancements. For example, as operating frequencies increase electrical parasitic effects plague electronic systems with intermittent errors. One such parasitic effect is simultaneous switching noise. More particularly, when many transistors or transistor cells switch at once on a chip or group of chips, there is an instantaneous demand for current from the power distribution system on the chips and the packages.
This high current demand may lead to voltage reduction on the power planes of the chips and packages and going less neutral on the reference planes as well as other detrimental effects. These simultaneous switching noise effects can be alleviated by substantially increasing the capacitance of the electronic package, as the stored charge in the capacitors can bolster the sagging supply voltage planes.
Typically, capacitance is added to an electronic package with discrete capacitor chips, in this regard, key areas of concern are capacitance, inductance, and cost. A preferred package will have high capacitance, low inductance, and low cost. While most common chip capacitors have fairly low cost and fairly high capacitance, they tend to have fairly high inductance. Other shortcomings of chip capacitors is the amount of space they take up on a single or multiple chip package and the time and cost to assemble a package including such a chip capacitor.
From a performance standpoint, the best capacitance is distributed capacitance, that is, capacitance that is integrated into large areas of the package. Examples of devices employing distributive capacitance are disclosed in U.S. Pat. Nos. 5,079,069; 5,155,655; 5,161,086; and 5,261,153. Distributed capacitance yields the lowest possible inductance and puts the capacitance nearly everywhere instead of at discrete points on an electronic package. This may be critical as certain parts of a chip that need de-coupling capacitance may be located too far from a discrete chip for the de-coupling to be effective. However, a shortcoming associated with existing distributed capacitance devices is that traditional approaches to distributed F w capacitance may give very small capacitance values in the range from tens of pico-faradslcm.sup.2 to possibly a few nano-farads/cm.sup.2. Unfortunately, systems designers often require tens to 100's of nano-faradslcm.sup.2 of capacitance per package.
Another feature that is of interest in packaging design is the inclusion of arrays of resistors. These resistors can be used to terminate transmission lines on the package and be tied to a voltage/reference plane in a capacitor structure. Again, these functions are typically provided by installing discrete resistors to the packaging, which, of course, creates many of the shortcomings associated with the use of discrete capacitors, such as space, performance, cost, and handling limitations.
Thin film resistors, such as Titanium-Tungsten (TiW) or Tantalum Nitride, may be employed to take up less space and to provide more even performance across the electronic package. While chip resistor arrays often have tolerances of .+-.15-30%, thin film resistors commonly have resistance tolerances of about .+-.1-5%. In addition to tighter tolerances, thin film resistors take up less space on the package and are integrated within the electronic package. No component assembly is required thus reducing assembly cost and increasing reliability or discrete components. However, a shortcoming with integrating thin film resistors into thin laminated structures is that the brittle resistor material may be subjected to stresses that will damage them during the flexing of an electronic package. This can make the already fragile thin, laminated package material even more sensitive to stress and more easily damaged.
The foregoing illustrates limitations known to exist in present electronic packages. Thus, a continuing need exists for improved electronic packages which overcome one or more of the limitations set forth above.